Multi-threaded core processors are dominant in most modern computer processor designs. One of the most useful techniques for testing computer processor designs involves generating an instruction sequence and expected results using a reference model of the computer processor design. The same instructions are then processed in a simulation using a hardware model of the computer processor design, where the actual results of the hardware simulation are compared with the expected results generated using the reference model. A mismatch for any instruction would indicate an error in the reference model, the hardware model, or both.
Testing multi-threaded core processor designs often involves testing instructions in different threads that access shared computer memory locations. The order in which such instructions are processed determines the state of computer memory locations and processor registers at any given point during instruction processing. Unfortunately, as the order in which the instructions of different threads in multi-threaded software applications is unknown before processing the instructions using a hardware model of a computer processor design under test, generating expected results for the instructions using a reference model in advance of hardware model simulation is challenging.